Graphics processor memory access architecture with address ordering

• Main Authors: KOKER ALTUG, RANGANATHAN VAITHEESWARAN, SHINDE, PARTHA, RAGHAVENDRA, GEORGE VARGHESE, NAVALE ADITYA, KRISHNAN VENKATESH, ASHBAUGH BEN J, FU FANGWEN, GANAPATHY, SRIVATSAN, RAY JOYDEEP, APPU ABHISHEK R
• Format: Patent
• Language: Chinese; English
• Published: 28.03.2023
• Subjects: CALCULATING; COMPUTING; COUNTING; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; PHYSICS

One embodiment provides a graphics processor comprising a processing resource comprising a register file, a memory, a cache, and a load/store/cache circuit for processing load, store, and prefetch messages from the processing resource. The circuitry will sort the received memory access messages into a read and written address sorting list. Circuitry schedules a first set of address ranking requests from a first request buffer for a first time period, and then schedules a second set of address ranking requests from a second request buffer for a second time period. 一个实施例提供一种图形处理器，该图形处理器包括：包含寄存器堆的处理资源，存储器，缓存，和用于处理来自处理资源的加载、存储和预取消息的加载/存储/缓存电路。电路将会将接收到的存储器访问消息排序到读取和写入的地址排序列表中。电路从第一请求缓冲器调度第一组地址排序请求达第一时间段，随后从第二请求缓冲器调度第二组地址排序请求达第二时间段。