FPGA (Field Programmable Gate Array) design method based on block design

• Main Authors: WANG XINCHEN, DONG ZHIDAN, YU JIAN, HUI FENG
• Format: Patent
• Language: Chinese; English
• Published: 20.12.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a field programmable gate array (FPGA) design method based on block design, which relates to an FPGA technology, and comprises the following steps of: adding a virtual port module which forms an input port or an output port of a target block to the target block of a local path comprising a cross-block path; the layout position of the virtual port module is determined according to the position of the winding framework on the periphery of the local chip area corresponding to the target block, so that timing constraint can be carried out on the local path of the cross-block path contained in each target block when each block is designed; according to the method, the requirement of full-path time delay of the block path can be met as soon as possible during full-chip integration, repeated solution and redesign in the full-chip integration stage are avoided, the defects of existing block design are overcome, the FPGA design efficiency is improved, and the advantages of the block design are