Chip pin test method for avoiding mutual interference of multiple signals
The invention discloses a chip pin test method capable of avoiding mutual interference of multiple signals, which comprises the following test steps of S1, carding pins on a chip to be tested, querying pin information, determining pin functions and classifying the pins, S2, presetting input and outp...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
13.12.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a chip pin test method capable of avoiding mutual interference of multiple signals, which comprises the following test steps of S1, carding pins on a chip to be tested, querying pin information, determining pin functions and classifying the pins, S2, presetting input and output parameters of the pins, S3, loading current test voltage to a plurality of pins of the chip within the same time, and S4, testing the pins of the chip according to the current test voltage. According to the method, the pins are classified, the input and output data range is preset, and one pin in the same type is selected for testing each time, so that the signals between the pins with the same function can be influenced, the test can be smoothly carried out when a plurality of signals are loaded at the same time, the pins can be replaced at a time, and a plurality of groups of data can be obtained; according to the pin testing method and device, the test data of each pin and the preset data can be obtained by c |
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Bibliography: | Application Number: CN202211112587 |