Three-frequency-division circuit
The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate circuit and a two-frequency-division circuit, the first clock end of the first D trigger is connected with a first clock signal; the first clock...
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Main Authors | , , , , |
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Format | Patent |
Language | Chinese English |
Published |
22.11.2022
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Abstract | The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate circuit and a two-frequency-division circuit, the first clock end of the first D trigger is connected with a first clock signal; the first clock input end of the second D trigger is connected with a second clock signal; the first output end of the first D trigger is connected with the first input end of the NOR gate circuit and is fed back to the first input end of the first D trigger and the third input end of the second D trigger; the first output end of the second D flip-flop is connected with the third input end of the NOR gate circuit and is fed back to the third input end of the first D flip-flop and the first input end of the second D flip-flop; the first output end of the NOR gate circuit is connected with a frequency-halving circuit, and the frequency-halving circuit carries out frequency-halving processing on the NOR gate signal; wherein the phas |
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AbstractList | The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate circuit and a two-frequency-division circuit, the first clock end of the first D trigger is connected with a first clock signal; the first clock input end of the second D trigger is connected with a second clock signal; the first output end of the first D trigger is connected with the first input end of the NOR gate circuit and is fed back to the first input end of the first D trigger and the third input end of the second D trigger; the first output end of the second D flip-flop is connected with the third input end of the NOR gate circuit and is fed back to the third input end of the first D flip-flop and the first input end of the second D flip-flop; the first output end of the NOR gate circuit is connected with a frequency-halving circuit, and the frequency-halving circuit carries out frequency-halving processing on the NOR gate signal; wherein the phas |
Author | PI CHANGMING WANG YANING ZHANG NANPING HUANG YAO YANG HAILING |
Author_xml | – fullname: ZHANG NANPING – fullname: PI CHANGMING – fullname: HUANG YAO – fullname: YANG HAILING – fullname: WANG YANING |
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DocumentTitleAlternate | 三分频电路 |
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Notes | Application Number: CN202211290241 |
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Snippet | The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate... |
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Title | Three-frequency-division circuit |
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