Three-frequency-division circuit

The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate circuit and a two-frequency-division circuit, the first clock end of the first D trigger is connected with a first clock signal; the first clock...

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Bibliographic Details
Main Authors ZHANG NANPING, PI CHANGMING, HUANG YAO, YANG HAILING, WANG YANING
Format Patent
LanguageChinese
English
Published 22.11.2022
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Summary:The invention provides a three-frequency-division circuit. The three-frequency-division circuit comprises a first D trigger, a second D trigger, a NOR gate circuit and a two-frequency-division circuit, the first clock end of the first D trigger is connected with a first clock signal; the first clock input end of the second D trigger is connected with a second clock signal; the first output end of the first D trigger is connected with the first input end of the NOR gate circuit and is fed back to the first input end of the first D trigger and the third input end of the second D trigger; the first output end of the second D flip-flop is connected with the third input end of the NOR gate circuit and is fed back to the third input end of the first D flip-flop and the first input end of the second D flip-flop; the first output end of the NOR gate circuit is connected with a frequency-halving circuit, and the frequency-halving circuit carries out frequency-halving processing on the NOR gate signal; wherein the phas
Bibliography:Application Number: CN202211290241