Error voltage elimination modulation method for hybrid device three-level split output inverter
The invention discloses a hybrid device three-level split output inverter error voltage elimination modulation method. The Si IGBT in the main circuit works at a low switching frequency, the SiC MOSFET works at a high switching frequency of 100 kHz, the SiC SBD Da2 and Da3 are used for current follo...
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Main Authors | , , , , , , |
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Format | Patent |
Language | Chinese English |
Published |
18.11.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a hybrid device three-level split output inverter error voltage elimination modulation method. The Si IGBT in the main circuit works at a low switching frequency, the SiC MOSFET works at a high switching frequency of 100 kHz, the SiC SBD Da2 and Da3 are used for current follow current, and the isolation inductor isolates and separates the SiC MOSFET. In the error voltage elimination modulation method, upper and lower laminated carrier waves and three-phase modulation waves are input into a pulse generation module for comparison, the pulse generation module outputs an initial driving signal, and an error voltage elimination module outputs a driving signal. And the low-pass filter filters high-frequency current harmonic waves in the output current to obtain output current fundamental waves. Modulation is carried out in four intervals according to the polarities of the modulation wave and the fundamental wave current. According to the hybrid device three-level split output inverter error |
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Bibliography: | Application Number: CN202210532193 |