Digital down-conversion design method of multiplication-free architecture

• Main Authors: CHEN TINGTING, ZHANG QINFENG, SHAO JIE, WAN SHUQIN, JIANG YINGDAN, WANG ZUJIN, GAO MIN, ZHUO LIN
• Format: Patent
• Language: Chinese; English
• Published: 08.11.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a digital down-conversion design method of a multiplication-free architecture, which belongs to the field of digital down-conversion, and comprises the following steps: inputting a digital intermediate frequency signal, down-converting an interested signal to a baseband through a frequency mixing module, completing a down-sampling function through a low-pass digital decimation filter module, and filtering out a high-frequency component at the same time. In broadband/narrowband channel multiplexing high-speed sampling, in order to reduce frequency mixing operation complexity, give consideration to subsequent signal processing and coordinate the relation between local oscillator signal frequency and radio frequency receiving system sampling frequency, the carrier frequency of an intermediate frequency signal is set to be fLO = fs/8, and an interested frequency band is reduced to a low frequency band; and performing multiphase decomposition on an integrator module in the CIC filter, and c