Semiconductor package with electromagnetic interference shielding

The embodiment of the invention relates to a semiconductor package with electromagnetic interference shielding. In one embodiment, a semiconductor package includes a multi-layer package substrate including a first layer including a first dielectric layer and a first metal layer, the first metal laye...

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Main Authors CHEN JIE, WAN LIANG, MURUGAN RAMANATHAN M, TANG YIQI
Format Patent
LanguageChinese
English
Published 01.11.2022
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Abstract The embodiment of the invention relates to a semiconductor package with electromagnetic interference shielding. In one embodiment, a semiconductor package includes a multi-layer package substrate including a first layer including a first dielectric layer and a first metal layer, the first metal layer including a first metal trace; and a second layer including a second dielectric layer. An integrated circuit (IC) die includes a bond pad, wherein a bottom side of the IC die is attached to the first metal trace. A metal guide pillar is connected to the first metal trace through the second dielectric layer. A third layer on the second layer includes: a third dielectric layer on the second layer extending to a bottom side of the semiconductor package; and a second metal layer including a second metal trace, the second metal trace including an inner second metal trace connected to the bond pad and an outer second metal trace over the metal pillar; and a filled via disposed outside of a reachable contact pad, the re
AbstractList The embodiment of the invention relates to a semiconductor package with electromagnetic interference shielding. In one embodiment, a semiconductor package includes a multi-layer package substrate including a first layer including a first dielectric layer and a first metal layer, the first metal layer including a first metal trace; and a second layer including a second dielectric layer. An integrated circuit (IC) die includes a bond pad, wherein a bottom side of the IC die is attached to the first metal trace. A metal guide pillar is connected to the first metal trace through the second dielectric layer. A third layer on the second layer includes: a third dielectric layer on the second layer extending to a bottom side of the semiconductor package; and a second metal layer including a second metal trace, the second metal trace including an inner second metal trace connected to the bond pad and an outer second metal trace over the metal pillar; and a filled via disposed outside of a reachable contact pad, the re
Author WAN LIANG
MURUGAN RAMANATHAN M
TANG YIQI
CHEN JIE
Author_xml – fullname: CHEN JIE
– fullname: WAN LIANG
– fullname: MURUGAN RAMANATHAN M
– fullname: TANG YIQI
BookMark eNqNjD0SgjAUBlNogT93iAewAERrhsGxstGeyTw-whvDC5PE8fpSeACrbXZ3o1biBZmqH5iYvPRvSj7o2dDLWOgPp1HDgVLwk7GCxKRZEsKAACHoODJcz2J3aj0YF7H_casO1_bZ3I6YfYe4HLHkXXPP86q4nM5FWZf_OF-IBzRS
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
DocumentTitleAlternate 具有电磁干扰屏蔽的半导体封装
ExternalDocumentID CN115274623A
GroupedDBID EVB
ID FETCH-epo_espacenet_CN115274623A3
IEDL.DBID EVB
IngestDate Fri Jul 19 14:29:09 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language Chinese
English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_CN115274623A3
Notes Application Number: CN202210453659
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221101&DB=EPODOC&CC=CN&NR=115274623A
ParticipantIDs epo_espacenet_CN115274623A
PublicationCentury 2000
PublicationDate 20221101
PublicationDateYYYYMMDD 2022-11-01
PublicationDate_xml – month: 11
  year: 2022
  text: 20221101
  day: 01
PublicationDecade 2020
PublicationYear 2022
RelatedCompanies TEXAS INSTRUMENTS INCORPORATED
RelatedCompanies_xml – name: TEXAS INSTRUMENTS INCORPORATED
Score 3.5638092
Snippet The embodiment of the invention relates to a semiconductor package with electromagnetic interference shielding. In one embodiment, a semiconductor package...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
Title Semiconductor package with electromagnetic interference shielding
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221101&DB=EPODOC&locale=&CC=CN&NR=115274623A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwY2BQsUxMNDdPM03STTUxT9M1STMHloPGqUm6wMooCZiGEqHjkL5-Zh6hJl4RphFMDFmwvTDgc0LLwYcjAnNUMjC_l4DL6wLEIJYLeG1lsX5SJlAo394txNZFDdo7NgJ1ZwzVXJxsXQP8Xfyd1ZydbZ391PyCbA1B17eaAOt6R2YGVlAzGnTOvmuYE2hXSgFyleImyMAWADQtr0SIgakqQ5iB0xl285owA4cvdMIbyITmvWIRYAEIWseenwc6oDW_SAHo7GxgWaAAGkhVgF5mk5uYngfalKgAOgSiCLqTT6E4A7RKDVhFiTIourmGOHvoAt0SD_d4vLMfwtnGYgwsefl5qRIMCsAeralFkkmqQYpJsom5aaqFJbCaNkgGVt2G5onmhiaSDFK4zZHCJynNwAUKRMheOxkGlpKi0lRZYKVbkiQHDi0Ae9CGNg
link.rule.ids 230,309,786,891,25594,76904
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1NT4NAEJ3Uaqw3rRqtX5gYbsTSLm57IMYuENRCG4Omt4ZFsGqEBjAm_npncWu96I1AspndMPMys_PeAJz1w5DSxOBaTGiikYRiHOzGXEMw4vgPhbIO6fkX7j25mRiTGrwsuDCVTuhHJY6IHhWhv5dVvJ4vi1hW1VtZnPNnfJVdOoFpqTI77oh0RletgWmPR9aIqYyZzFf9O1MX41sJYv3VCqxSTAmFzr79MBCslPlvSHE2YW2Mq6XlFtQ-Z01osMXktSase_LCGx-l7xXbGABFH3uWCoHWLFfQ7FeMBYoopCpymM1b-JQKUqIiRCByyeRTipnoUkOI2oFTxw6Yq6Et05-NT5m_NLu7C_U0S-M9UDCjNXqcxO1HEhFqxL0-wnQ7QujWaUh1sg-tv9dp_ffxBBpu4A2nw2v_9gA2xIF-8-4OoV7m7_ERAnDJj6uT-wLpI4kh
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=Semiconductor+package+with+electromagnetic+interference+shielding&rft.inventor=CHEN+JIE&rft.inventor=WAN+LIANG&rft.inventor=MURUGAN+RAMANATHAN+M&rft.inventor=TANG+YIQI&rft.date=2022-11-01&rft.externalDBID=A&rft.externalDocID=CN115274623A