Physical verification method for integrated circuit layout design, electronic equipment and storage medium

• Main Authors: JIANG SHENGFENG, FAN WENQI
• Format: Patent
• Language: Chinese; English
• Published: 28.10.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a physical verification method for integrated circuit layout design, electronic equipment and a storage medium. The method comprises the following steps: modifying a rule file for physical verification into a general rule file in an adaptive manner; constructing a running environment of the physical verification tool; checking whether a configuration file exists or not when the physical verification tool is started, wherein the configuration file is used for realizing configuration of a plurality of options in the rule file; calling the general rule file under the condition that the configuration file exists, and executing physical verification according to the configuration file, the integrated circuit layout design information and the general rule file; and generating a verification result file and outputting the verification result file to a specified position, and if the configuration file cannot be checked when the physical verification tool is started, prompting to select a plura