Field effect transistor performance analysis method and layout optimization method

• Main Author: JIANG SHENGFENG
• Format: Patent
• Language: Chinese; English
• Published: 28.10.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a field effect transistor performance analysis method and a layout optimization method. The field effect transistor performance analysis method comprises the following steps: adding a polysilicon spacing parameter into a standard device symbol to obtain a circuit netlist with polysilicon spacing parameter information; the field effect transistor model is adopted to conduct simulation according to the circuit netlist with the polycrystalline silicon spacing parameter information so as to obtain performance parameters of the field effect transistor, and the performance analysis method of the field effect transistor further comprises the step of converting the polycrystalline silicon spacing parameter into an equivalent channel parameter. According to the method for analyzing the performance of the field effect transistor, the polycrystalline silicon spacing effect of the field effect transistor is analyzed by adopting an existing field effect transistor model, so that the influence of th