Link delay measurement method and system
The invention relates to a link delay measurement method and system. The measurement method comprises the following steps: generating a first 2n-phase clock at a host end; sampling the second pulse signal; reading a sampling result, and selecting an optimal sampling clock; using the optimal sampling...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
25.10.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The invention relates to a link delay measurement method and system. The measurement method comprises the following steps: generating a first 2n-phase clock at a host end; sampling the second pulse signal; reading a sampling result, and selecting an optimal sampling clock; using the optimal sampling clock as a sending clock to send a synchronization sequence to the slave end; the slave end forwards the synchronization sequence back to the host end; performing clock recovery and generating a second 2n-phase clock; sampling the second pulse signal through a second 2n-phase clock; reading out a sampling result, and selecting a clock corresponding to a fractional order; according to the phase of the clock corresponding to the fractional order, calculating fractional order delay; calculating integer-order delay according to the number of the spaced sampling clocks; and adding the integer-order delay and the fractional-order delay to obtain the overall delay of the link. The measuring system is used for executing t |
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Bibliography: | Application Number: CN202210853343 |