Multi-chip stacking packaging structure and packaging method

• Main Author: YAO DAPING
• Format: Patent
• Language: Chinese; English
• Published: 25.10.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

The invention provides a multi-chip stacked packaging structure, which comprises a circuit substrate, a plurality of chips and a plurality of chips, the first chip is positively arranged on one side of the circuit substrate, the first chip comprises a first chip body, a first rewiring structure located on the surface of the side, away from the circuit substrate, of the first chip body and a first bonding pad, and the first bonding pad is located on the surface of a partial edge area of the side, away from the first chip body, of the first rewiring structure; the second chip is inversely arranged on the side, away from the circuit substrate, of a part of the first chip, and the second chip comprises a second chip body, a second rewiring structure located on the surface of the side, facing the circuit substrate, of the second chip body, and a second bonding pad; the second bonding pad is located on the surface of a partial edge area of one side, deviating from the second chip body, of the second rewiring struct