Multi-core packet network processor architecture and task scheduling method

• Main Authors: YUAN DEPENG, ZHANG SHUANGLIN
• Format: Patent
• Language: Chinese; English
• Published: 14.10.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention provides a multi-core packet network processor architecture and a task scheduling method. The architecture comprises a plurality of message processor core groups connected to a bus; each message processor core group comprises a task buffer area, a task distributor and a plurality of message processor cores which are connected in parallel, the task buffer area is used for temporarily storing to-be-distributed tasks from a bus, and the task distributor periodically queries the task buffer area; task decomposition is carried out on the tasks in the task buffer area, the tasks are sequentially distributed to the message processor cores in the message processor core group, and the multiple message processor cores which are connected in parallel are used for processing the tasks of the same type respectively; and the message processor cores in the message processor core group output a next-level task to the bus, the next-level task is transmitted to the task buffer area of the message processor core g