Top-down layout hierarchical structure processing method and device and storage medium

• Main Authors: ZHOU JIEYUN, ZHOU QUNBO, WANG LIANG, YU YITIAN, CHEN XUELIAN, PENG HUIXIN, CUI SHAOCHUN
• Format: Patent
• Language: Chinese; English
• Published: 27.09.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention relates to the technical field of integrated circuit layouts, in particular to a top-down layout hierarchical structure processing method and device and a storage medium, and can solve the problem of large calculated amount in the processing process of an integrated circuit layout to a certain extent. According to the embodiment of the invention, a bounding box of each initial unit is obtained from an initial integrated circuit layout; the target unit can be screened from the initial units based on the area of each bounding box; effective instances are further screened out from all the first instances of the target unit, the effective instances are located in an upper layer unit of the target unit, and the target integrated circuit layout can be determined on the basis of a reusable area of the effective instances, and the reusable area is a non-overlapping area of the effective instances and second instances in the upper layer unit. 本申请涉及集成电路版图技术领域，具体而言，涉及一种自顶向下的版图层次结构处理方法、装置及存储介质，一定程度上可以解决集成电路