High performance phase locked loop

• Main Author: TAYARI, AMIN
• Format: Patent
• Language: Chinese; English
• Published: 20.09.2022
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRICITY

The invention discloses a high-performance phase-locked loop, comprising: a plurality of partial phase comparators for: obtaining at least one reference signal phase and obtaining a plurality of local oscillator signal phases; forming at least three partial phase error signals, where each partial phase error signal is formed by comparing a phase of the at least one reference signal phase with a respective phase of the plurality of local oscillator signal phases; applying a respective weighting factor to each of the at least three partial phase error signals, where each weighting factor is selected from a matrix weighting factor configuration associated with a phase offset between a reference signal and a local oscillator signal; and a summing circuit for generating a composite phase error signal by analog summing the plurality of partial phase error signals, and responsively adjusting the fixed phase of the local oscillator by the composite phase error signal. 本发明公开一种高性能锁相环，包括：多个部分相位比较器，用于：获取至少一个参考信号相位以及获取多个本