FPGA (Field Programmable Gate Array) layout method implemented based on layout range constraint of IP (Internet Protocol) core

• Main Authors: JIANG SHAN, WANG XINCHEN, DONG ZHIDAN, LI QING, YU JIAN, HUI FENG
• Format: Patent
• Language: Chinese; English
• Published: 20.09.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses an FPGA (Field Programmable Gate Array) layout method implemented based on layout range constraints of IP (Internet Protocol) cores, and relates to the technical field of FPGAs, the method comprises the following steps: firstly, determining the layout range of the IP cores according to an IP subnet list and IP performance constraints of each IP core for an FPGA with a built-in IP core, and then, under the condition that the IP subnet list of each IP core is subjected to layout wiring in the corresponding layout range, determining the layout range of each IP core according to the layout range of each IP core. And carrying out global layout and wiring on the input netlist on the FPGA based on the user design constraint and the respective IP performance constraint of each IP core. By pre-determining the layout range of the IP core as the constraint, it can be ensured that the IP performance constraint can be achieved when the IP core is laid out in the corresponding layout range, the IP p