Design method for sub-array driving self-excitation self-adaptive processing

The invention discloses a design method for sub-array driving self-excitation self-adaptive processing, which comprises the following steps of: arranging an amplifying circuit at a transmitting-receiving channel and a transmitting-receiving port of a TR (Transmitter-Receiver) component, arranging a...

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Bibliographic Details
Main Authors SUN JUN, MA FUBO
Format Patent
LanguageChinese
English
Published 02.09.2022
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Summary:The invention discloses a design method for sub-array driving self-excitation self-adaptive processing, which comprises the following steps of: arranging an amplifying circuit at a transmitting-receiving channel and a transmitting-receiving port of a TR (Transmitter-Receiver) component, arranging a directional coupler and a detector at the transmitting-receiving port to acquire voltage, inputting the voltage into a peak holding circuit, obtaining voltage Vdet when self-excitation is generated, inputting the voltage Vdet into a logic control circuit through an AD (Analog to Digital) conversion circuit, and if the Vdet is greater than a set value, outputting the self-excitation self-adaptive processing. If the sub-array driving TR assembly is in a self-checking working mode, judging that a fault occurs, generating a power supply control enable signal PEN, inputting an amplification circuit, closing a fault channel, judging whether a self-excitation fault exists in the TR assembly connected with the sub-array dr
Bibliography:Application Number: CN202210462857