SEMICONDUCTOR MEMORY DEVICE

Embodiments provide a semiconductor memory device in which a step portion is easy to form. A semiconductor memory device (10) according to an embodiment is provided with: a lamination unit (100) in which a plurality of conductor layers (40) are laminated in a z direction; and a step section (200) fo...

Full description

Saved in:
Bibliographic Details
Main Authors IINO HIROMITSU, NOJIMA KAZUHIRO, TAKESHITA SHUNPEI, YAMAMOTO NAOKI
Format Patent
LanguageChinese
English
Published 30.08.2022
Subjects
Online AccessGet full text

Cover

Loading…
Abstract Embodiments provide a semiconductor memory device in which a step portion is easy to form. A semiconductor memory device (10) according to an embodiment is provided with: a lamination unit (100) in which a plurality of conductor layers (40) are laminated in a z direction; and a step section (200) for drawing out the plurality of conductor layers (40) in a step shape in the y direction. The step portion (200) includes a lower step portion (220) and an upper step portion (210). The upper step section (210) is formed such that the conductor layer (40) extends further toward one side in the y direction as the conductor layer (40) travels toward the lower step section (220) in the z direction. The lower step section (220) is formed on the opposite side from the one side in the y direction than the upper step section (210). 实施方式提供一种容易形成阶梯部的半导体存储装置。实施方式的半导体存储装置10具备:积层部100,将多个导电体层40沿z方向积层;及阶梯部200,将多个导电体层40沿y方向阶梯状引出。阶梯部200中包含着下侧阶梯部220与上侧阶梯部210。在上侧阶梯部210中,以沿z方向越朝下侧阶梯部220侧行进,导电体层40朝沿y方向的一侧延伸得越长的方式形成。下侧阶梯部220形成在比上侧阶梯部210
AbstractList Embodiments provide a semiconductor memory device in which a step portion is easy to form. A semiconductor memory device (10) according to an embodiment is provided with: a lamination unit (100) in which a plurality of conductor layers (40) are laminated in a z direction; and a step section (200) for drawing out the plurality of conductor layers (40) in a step shape in the y direction. The step portion (200) includes a lower step portion (220) and an upper step portion (210). The upper step section (210) is formed such that the conductor layer (40) extends further toward one side in the y direction as the conductor layer (40) travels toward the lower step section (220) in the z direction. The lower step section (220) is formed on the opposite side from the one side in the y direction than the upper step section (210). 实施方式提供一种容易形成阶梯部的半导体存储装置。实施方式的半导体存储装置10具备:积层部100,将多个导电体层40沿z方向积层;及阶梯部200,将多个导电体层40沿y方向阶梯状引出。阶梯部200中包含着下侧阶梯部220与上侧阶梯部210。在上侧阶梯部210中,以沿z方向越朝下侧阶梯部220侧行进,导电体层40朝沿y方向的一侧延伸得越长的方式形成。下侧阶梯部220形成在比上侧阶梯部210
Author TAKESHITA SHUNPEI
IINO HIROMITSU
YAMAMOTO NAOKI
NOJIMA KAZUHIRO
Author_xml – fullname: IINO HIROMITSU
– fullname: NOJIMA KAZUHIRO
– fullname: TAKESHITA SHUNPEI
– fullname: YAMAMOTO NAOKI
BookMark eNrjYmDJy89L5WSQDnb19XT293MJdQ7xD1LwdfX1D4pUcHEN83R25WFgTUvMKU7lhdLcDIpuriHOHrqpBfnxqcUFicmpeakl8c5-hoYmluamJqZGjsbEqAEANhQidA
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
DocumentTitleAlternate 半导体存储装置
ExternalDocumentID CN114975452A
GroupedDBID EVB
ID FETCH-epo_espacenet_CN114975452A3
IEDL.DBID EVB
IngestDate Fri Aug 16 05:56:21 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language Chinese
English
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_CN114975452A3
Notes Application Number: CN202111004087
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220830&DB=EPODOC&CC=CN&NR=114975452A
ParticipantIDs epo_espacenet_CN114975452A
PublicationCentury 2000
PublicationDate 20220830
PublicationDateYYYYMMDD 2022-08-30
PublicationDate_xml – month: 08
  year: 2022
  text: 20220830
  day: 30
PublicationDecade 2020
PublicationYear 2022
RelatedCompanies TOSHIBA MEMORY CORPORATION
RelatedCompanies_xml – name: TOSHIBA MEMORY CORPORATION
Score 3.549074
Snippet Embodiments provide a semiconductor memory device in which a step portion is easy to form. A semiconductor memory device (10) according to an embodiment is...
SourceID epo
SourceType Open Access Repository
SubjectTerms ELECTRICITY
Title SEMICONDUCTOR MEMORY DEVICE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220830&DB=EPODOC&locale=&CC=CN&NR=114975452A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1NS8Mw9DGnqDedim4qFaS3Yuy6tjsUcUnKFNqOuo15Gknaoh50uIrgr_c1dM6L3kIevCQP3mfeB8Clko4rUNFbKP2V5aBJYok-6VrK9vysKIqeyHW2RewOJ879rDdrwMuqFkb3Cf3UzRGRoxTye6nl9WIdxGI6t3J5JZ9x6-0mHAfMrL1j20aLgphsEPBRwhJqUhrQ2IzTAM3-vlfN077dgE00o70q_YtPB1VVyuK3Sgn3YGuE2F7LfWh8PbVgh64mr7VgO6o_vHFZ897yADoPFcmSmE3oOEmNiEdJ-mgwPr2j_BAuQj6mQwtPmf88aU7j9YW6R9BEVz8_BsPOVCauBckUcRBEpFfkQhbK91VB3EyeQPtvPO3_gB3Yrcijo6HkFJrl-0d-huq0lOeaDt87nXaO
link.rule.ids 230,309,783,888,25578,76884
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR3LToNAcFKrsd60arT1gYnhRlwpBXogxi4QqgUapE09EXaBqAdtLMbEr3fYUOtFb5udZHZ3knnuPAAuOdP0FBW9gtKfKxqaJEo6ID2Fq4aZFUXRT3ORbRHo3lS7m_fnDXhZ1cKIPqGfojkichRHfi-FvF6sg1i2yK1cXrFn3Hq7cWPLlmvvWFXRoiCyPbScSWiHVKbUooEcRBaa_QOjmqd9uwGbaGKbVZ99ZzasqlIWv1WKuwtbE8T2Wu5B4-upDS26mrzWhm2__vDGZc17y33oPlQkCwN7SuMwknzHD6NHyXZmI-ocwIXrxNRT8JTk50kJDdYX6h1CE139_AgkNeNZep2SjBMNQYQZRZ6ygpsmL4iesWPo_I2n8x_wHFpe7I-T8Si478JORSoRGSUn0CzfP_JTVK0lOxM0-QbyCnl-
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=SEMICONDUCTOR+MEMORY+DEVICE&rft.inventor=IINO+HIROMITSU&rft.inventor=NOJIMA+KAZUHIRO&rft.inventor=TAKESHITA+SHUNPEI&rft.inventor=YAMAMOTO+NAOKI&rft.date=2022-08-30&rft.externalDBID=A&rft.externalDocID=CN114975452A