Integrated heterojunction bipolar transistor and manufacturing method thereof
The invention discloses an integrated heterojunction bipolar transistor and a manufacturing method thereof, which belong to the technical field of semiconductors, and are characterized in that during mesa etching, an epitaxial layer and a dielectric layer of a preset capacitance area of a passive ar...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
30.08.2022
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses an integrated heterojunction bipolar transistor and a manufacturing method thereof, which belong to the technical field of semiconductors, and are characterized in that during mesa etching, an epitaxial layer and a dielectric layer of a preset capacitance area of a passive area are reserved, and during subsequent manufacturing of collector contact metal, the epitaxial layer and the dielectric layer of the preset capacitance area of the passive area are reserved; and synchronously forming a metal electrode plate on the dielectric layer in the preset area to manufacture a passive device structure. According to the invention, on the premise of not increasing additional processes, the problem of element diffusion caused by contact between the metal electrode plate and the GaAs epitaxial layer is avoided, the flatness of the metal electrode plate is maintained, and the performance of the passive device structure is improved.
本发明公开了一种集成异质结双极晶体管及其制作方法,属于半导体的技术领域,是在进行台面蚀刻时,保留无源区的预设电容区域的外延层和介质层 |
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Bibliography: | Application Number: CN202210908826 |