METHOD AND APPARATUS FOR PROVIDING SERDES BLOCKS FOR FPGA FACILITATING HIGH SPEED DATA

• Main Authors: JENNINGS GRANT THOMAS, WANG TIANPING, LIN XIAOZHI
• Format: Patent
• Language: Chinese; English
• Published: 17.05.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The application discloses a system including a host and a device having a field programmable gate array (FPGA). The system includes a set of configurable logic blocks (LBs), a bus, and a Universal Serial Bus (USB) interface. In one aspect, the configurable LB can be selectively programmed to perform one or more logic functions. The bus includes a P-channel and an N-channel for transmitting signals according to a high-speed USB protocol. The USB interface is configured to include a first differential comparator for identifying a logical 0 state at a P channel and a second differential comparator for identifying a logical 0 state at an N channel. 本申请公开了一种包含主机和具有现场可编程门阵列(FPGA)的设备的系统。该系统包括一组可配置逻辑块(LB)、总线和通用串行总线(USB)接口。在一个方面，该可配置LB能够被选择性地编程以执行一个或多个逻辑功能。该总线包含用于根据高速USB协议传输信号的P通道和N通道。该USB接口被配置为包括用于识别P通道处的逻辑0状态的第一差分比较器和用于识别N通道处的逻辑0状态的第二差分比较器。