Sorting and testing integrated chip FT testing system and method

• Main Authors: WANG JIANQIN, WU XINLONG, CHEN RONG
• Format: Patent
• Language: Chinese; English
• Published: 29.03.2022
• Subjects: PERFORMING OPERATIONS; POSTAL SORTING; SEPARATING SOLIDS FROM SOLIDS; SORTING; SORTING INDIVIDUAL ARTICLES, OR BULK MATERIAL FIT TO BE SORTEDPIECE-MEAL, e.g. BY PICKING; TRANSPORTING

The invention relates to a chip FT test system integrating sorting and testing. The chip FT test system comprises a test host, a sorting machine and a chip to be tested, a plurality of ADC test ports are integrated in the test host; the sorting machine has basic functions of picking up and placing chips to be tested; the chip to be tested is provided with a corresponding test port; signals are transmitted between the testing host and the sorting machine in a TTL level signal mode. The chip to be detected provides a visual direction signal for the sorting machine through the visual sensor; the sorting machine is used for grabbing, placing and adjusting the direction of a to-be-detected chip; the test host detects the to-be-tested chip, and the to-be-tested chip feeds back a detection result to the test host for processing. According to the invention, the electrical function of the chip can be visually tested, and screening and classification are carried out, so that the chip testing and editing cost is effecti