Interconnection system fence mechanism

• Main Authors: KOKER ALTUG, PUFFER DAVID, RANGANATHAN VAITHEESWARAN, VALERIO JAMES, SHAH ANKUR, BOLES JEFFERY S, NALLURI HARISH CHAND, RAY JOYDEEP, NAVALE, ABHISHEK, COORAY NIRANJAN L, RAMADOSS, MICHAEL, ANANTARAMAN ARAVINDH
• Format: Patent
• Language: Chinese; English
• Published: 08.03.2022
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; PHYSICS

The invention discloses an interconnection system fence mechanism. An apparatus that facilitates a memory barrier is disclosed. The apparatus includes an interconnect, a device memory, a plurality of processing resources coupled to the device memory to execute a plurality of execution threads as memory data producers and memory data consumers to the device memory and system memory, and fence hardware coupled to the device memory. The fence hardware is used to generate fence operations to enforce data ordering of memory operations published to system memory and the device memory coupled via the interconnect. 本公开的发明名称为"一种互连系统栅栏机构"。公开一种促进存储器屏障的设备。该设备包括互连、装置存储器、多个处理资源以及栅栏硬件，所述多个处理资源耦合到装置存储器，以作为到装置存储器和系统存储器的存储器数据生产者和存储器数据消费者执行多个执行线程，所述栅栏硬件用于生成栅栏操作以对发布到经由所述互连耦合的系统存储器和所述装置存储器的存储器操作强制执行数据排序。