Method and Apparatus for Vertical Layered Decoding of Quasi-Cyclic Low-Density Parity Check Codes Built from Clusters of Circulant Permutation Matrices

• Main Authors: DECLERCQ DAVID, YELLA VAMSI KRISHNA, REYNWAR BENEDICT J
• Format: Patent
• Language: Chinese; English
• Published: 10.12.2021
• Subjects: BASIC ELECTRONIC CIRCUITRY; CODE CONVERSION IN GENERAL; CODING; DECODING; ELECTRICITY

The present disclosure relates to a method and an apparatus for vertical layered decoding of quasi-cyclic low-density parity check codes built from clusters of circulant permutation matrices. This invention presents a method and the corresponding hardware apparatus for decoding LDPC codes using a vertical layered (VL) iterative message passing algorithm. The invention operates on quasi-cyclic LDPC (QC-LDPC) codes, for which the non-zero circulant permutation matrices (CPMs) are placed at specific locations in the parity-check matrix of the codes, forming concentrated clusters of CPMs. The purpose of the invention is to take advantage of the organization of CPMs in clusters in order to derive a specific hardware architecture, consuming less power than the classical VL decoders. This is achieved by minimizing the number of read and write accesses to the main memories of the design. 本公开涉及一种用于从循环置换矩阵的集群构建的准循环低密度奇偶校验码的垂直分层解码的方法及设备。本发明呈现一种用于使用垂直分层VL迭代消息传递算法对LDPC码进行解码的方法及对应硬件设备。本发明对准循环QC LDPC码进行操作，对于所述准循环QC LDPC码，非零