Modularized semi-customized FPGA chip design method completed by means of automatic tool

• Main Authors: YANG HAIGANG, SHU YI, ZHAO FEI, QIU XIAOQIANG, JIA YIPING
• Format: Patent
• Language: Chinese; English
• Published: 07.12.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention relates to a modular semi-customized FPGA chip design method completed by an automatic tool, and belongs to the technical field of chip design. The method comprises the following steps: 1) completing a description file of a chip architecture; the description file needs to comprise process parameters, resource block distribution, time sequence constraint information and other to-be-customized overall architecture information; 2) analyzing the architecture file to generate a formatted integrated circuit netlist and a time sequence constraint file; 3) calling a resource block library file; 4) adding a customization unit; 5) performing comprehensive layout wiring; and 6) generating a board pattern. According to the method, on the basis of the expandability of the internal resources of the FPGA, designers can freely expand or cut the internal resources of the FPGA according to a specific application scene, the FPGA chip is rapidly customized, the chip design time is shortened, and the optimal area, p