APPARATUS AND METHOD FOR DYNAMIC CONTROL OF MICROPROCESSOR CONFIGURATION

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical proc...

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Main Authors GORBATOV EUGENE, VARMA ANKUSH, GUPTA NITIN, SISTLA KRISHNAKANTH, SRINIVASAN VIDYA, WEISSMANN ELIEZER, PALIT NILANJAN, KARHU ABHINAV
Format Patent
LanguageChinese
English
Published 28.09.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in respon
Bibliography:Application Number: CN202011478410