PAGE BUFFER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE PAGE BUFFER

The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line...

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Bibliographic Details
Main Authors PARK KANG-WOO, CHAI SOO-YEOL
Format Patent
LanguageChinese
English
Published 17.09.2021
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Summary:The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation. 本技术涉及一种页缓冲器和包括页缓冲器的半导体存储器装置。页缓冲器包括:第一锁存电路,其被配置为存储与第一编程状态和第二编程状态中的一个编程状态相对应的数据;位线控制器,其被连接至存储器块的位线,并且在编程验证操作中的位线预充电操作期间,通过根据存储在第一锁存电路中的数据向位线施加第一设置电压和第二设置电压中的一个设置电压,对位线进行预充电;以及第二锁存电路,通过主感测节点连接至位线控制器,并且被配置为在编程验证操作期间根据主感测节点的电位水平感测第一验证数据。
Bibliography:Application Number: CN202011098163