On-chip jitter evaluation for SerDes

• Main Authors: SUN JUNQING, QIAN HAOLI
• Format: Patent
• Language: Chinese; English
• Published: 06.08.2021
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

An illustrative integrated circuit and method providing on-chip jitter evaluation. One illustrative integrated circuit embodiment includes a digital receiver having a timing recovery circuit that determines a phase offset signal from estimated timing errors of previous sampling instants; and an on-chip memory that captures the phase offset signal, the on-chip memory being coupled to a processor that derives one or more jitter measurements from the phase offset signal. For initial calibration, the processor may configure the receiver for loop back operation, and thereafter the calibration values may enable evaluation of remote transmitter clock jitter. 一种提供片上抖动评估的说明性集成电路和方法。一个说明性集成电路实施例包括：具有定时恢复电路的数字接收器，定时恢复电路由先前采样时刻的估计的定时误差来确定相位偏移信号；以及捕获相位偏移信号的片上存储器，片上存储器被耦合到处理器，处理器从相位偏移信号中导出一个或多个抖动测量结果。为了初始校准，处理器可以将接收器配置成用于回送操作，并且此后，校准值可以实现对远程发射器时钟抖动的评估。