Reconfigurable array optimization method and automatic tuning method of hardware accelerator

The invention discloses a reconfigurable array optimization method and an automatic tuning method of a hardware accelerator, and belongs to the technical field of neural network tensor accelerator design engineering. The optimization method comprises the steps that hardware parameters suitable for p...

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Bibliographic Details
Main Authors GAO FAN, ZHU XIAORAN, CHANG HAN, DING HAN, HUANG HANTING, ZHU LEI, CHANG FAN, MEI KUIZHI, ZHAO YINGHAI, HUANG CHENGDONG
Format Patent
LanguageChinese
English
Published 06.08.2021
Subjects
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The invention discloses a reconfigurable array optimization method and an automatic tuning method of a hardware accelerator, and belongs to the technical field of neural network tensor accelerator design engineering. The optimization method comprises the steps that hardware parameters suitable for passive change serve as outer layer parameters, and hardware parameters suitable for active change serve as inner layer parameters; the outer layer parameters are an input channel, an output channel and an integer bit width; and the inner layer parameters are a logic core, a mode mask and a unit mask. The automatic tuning method comprises the following steps of: aiming at an outer layer parameter, setting a corresponding register position in application level switching, and finishing optimal hardware configuration of each application; and aiming at inner layer parameters, adopting a compiler + interpreter mode, finishing zero filling optimization by setting a logic kernel number and a mode mask, and finishing groupi
Bibliography:Application Number: CN202110548117