Semiconductor package and method of forming same

• Main Authors: HOU SHANGYONG, HUANG BINGGANG, QIU SHAOLING, LYU ZONGYU
• Format: Patent
• Language: Chinese; English
• Published: 06.07.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

An embodiment includes the steps of: partially forming a first via in a substrate of an interposer, the first via extending to a first side of the substrate of the interposer. The method further includes the steps of: bonding a first die to a first side of the substrate of the interposer. The method further includes the steps of: recessing a second side of the substrate of the interposer to expose a first via protruding from the second side of the substrate of the interposer, where after recessing, a thickness of the substrate of the interposer is less than 50 [mu]m. The method further includes thesteps of: forming a first set of conductive bumps on a second side of the substrate of the interposer, at least one of the first set of conductive bumps electrically coupled to the exposed first vias. The embodiment of the invention also relates to a semiconductor package and a method of forming the same. 实施例包括在中介层的衬底中部分地形成第一通孔，该第一通孔延伸到中介层的衬底的第一侧。该方法还包括将第一管芯接合到中介层的衬底的第一侧。该方法还包括使中介层的衬底的第二侧凹进以暴露第一通孔，第一通孔从中介层的衬底的第二侧突出，