Real-time transmission implementation system and method for reducing BUFG resources based on FPGA

The invention provides an FPGA-based real-time transmission implementation system for reducing BUFG resources, which comprises a main control module and an auxiliary module, and is characterized in that the main control module is connected with the auxiliary module; the main control module comprises...

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Bibliographic Details
Main Authors SHI LINYAN, ZHOU HE, JIA YUNFEI
Format Patent
LanguageChinese
English
Published 11.06.2021
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:The invention provides an FPGA-based real-time transmission implementation system for reducing BUFG resources, which comprises a main control module and an auxiliary module, and is characterized in that the main control module is connected with the auxiliary module; the main control module comprises a high-speed acquisition board, a signal processing board and a time sequence control board, the high-speed acquisition board is connected with the signal processing board, and the signal processing board is connected with the time sequence control board; the auxiliary module comprises a power supply module, a board card and a case backboard; a data external interface, a synchronous clock interface and a radio frequency clock interface are arranged on the case backboard, a detection board is arranged on the auxiliary module, the detection board comprises a first summarizing chip, a second summarizing chip, a third summarizing chip and a fourth summarizing chip, and the fourth summarizing chip generates the BUFG st
Bibliography:Application Number: CN202110264459