Bias method for matching circuit in large voltage margin range

• Main Authors: LIU HAITAO, XU HONGLIN, ZHANG LIZHEN, SHEN YIHUA
• Format: Patent
• Language: Chinese; English
• Published: 28.05.2021
• Subjects: CONTROLLING; PHYSICS; REGULATING; SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES

The invention relates to a bias method for matching a circuit in a large voltage margin range. The method involves a main circuit and a bias generation circuit, the main circuit comprises transistors M1 and M2, and a power supply Vdd is grounded through a resistor R, and the transistors M2 and M1 in sequence; the bias generation circuit comprises transistors M3-M6, the power supply Vdd is grounded through a current mirror I0 and the transistors M4 and M3 in sequence, and the power supply Vdd is grounded through a current mirror I2 and the transistors M6 and M5 in sequence; and the bias circuit is provided with a voltage margin boosting circuit, the voltage margin boosting circuit comprises a resistor Rs and current sources Is, the resistor Rs is connected between the drain electrode of the transistor M4 and the grid electrode of the transistor M3 in series, the current sources Is are connected in series in the vertical direction of the resistor Rs, a transistor Mx is inserted between transistors M5 and M6, an