ELECTRONIC SYSTEMS, FAULT DETECTING METHODS THEREOF, SYSTEM ON CHIPS, AND BUS SYSTEMS

• Main Authors: BHATTACHARYA ROHITASWA, LEE CHEON-SU
• Format: Patent
• Language: Chinese; English
• Published: 14.05.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

An electronic system may include one or more units of processing circuitry configured to implement a main intellectual property (IP), a checker IP, and an error detection circuit. The main IP includes a first data path and a first control signal path. The checker IP includes a second control signal path. The error detection circuit is configured to detect an error of data by performing error correction code (ECC) decoding of output data that is output by the main IP to the error detection circuit through the first data path, and detect an error of a control signal based on a first signal that is output by the main IP to the error detection circuit through the first control signal path, and a second signal that is output by the checker IP to the error detection circuit through the second control signal path. 公开了一种电子系统，可以包括被配置为实现主知识产权(IP)、检查器IP和错误检测电路的一个或多个处理电路单元。主知识产权IP包括第一数据路径和第一控制信号路径。检查器IP包括第二控制信号路径。错误检测电路被配置为：通过对由主IP通过第一数据路径输出到错误检测电路的输出数据执行纠错码(ECC)解码，来检测数据的错误，并且基于以下项来检测控制信号的错误：第一信号，由主IP通过第一控制信号路径输出到错误检测电路，