USING LOOP EXIT PREDICTION TO ACCELERATE OR SUPPRESS LOOP MODE OF A PROCESSOR

• Main Authors: ANNAMALAI ARUNACHALAM, EVERS MARIUS, THYAGARAJAN APARNA, JARVIS ANTHONY
• Format: Patent
• Language: Chinese; English
• Published: 30.04.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

A processor (100) predicts a number of loop iterations (115) associated with a set of loop instructions. In response to the predicted number of loop iterations exceeding a first loop iteration threshold, the set of loop instructions are executed in a loop mode that includes placing at least one component (105) of an instruction pipeline (114) of the processor in a low-power mode or state and executing the set of loop instructions from a loop buffer (109). In response to the predicted number of loop iterations being less than or equal to a second loop iteration threshold, the set of loop instructions are executed in a non-loop mode that includes maintaining at least one component of the instruction pipeline in a powered up state and executing the set of loop instructions from an instruction fetch unit (103) of the instruction pipeline. 处理器(100)预测与一组循环指令相关联的循环迭代的次数(115)。响应于所述预测的循环迭代次数超过第一循环迭代阈值，在循环模式下执行所述一组循环指令，所述循环模式包括将所述处理器的指令流水线(114)的至少一个部件(105)置于低功率模式或状态下和执行来自循环缓冲器(109)的所述一组循环指令。响应于所述预测的循环迭代次数小于或等于第二循环迭代阈值，