Synchronization signal generation circuit based on time competition
The invention discloses a synchronization signal generation circuit based on time competition, and the circuit comprises a control chip which is used for capturing a rising edge of a Syn signal through rising edge interruption input, outputting a PWM signal through a PWM output port of the control c...
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Main Authors | , , |
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Format | Patent |
Language | Chinese English |
Published |
19.03.2021
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Subjects | |
Online Access | Get full text |
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Summary: | The invention discloses a synchronization signal generation circuit based on time competition, and the circuit comprises a control chip which is used for capturing a rising edge of a Syn signal through rising edge interruption input, outputting a PWM signal through a PWM output port of the control chip, and outputting a signal CTLTri through an I/O output port of the control chip for controlling the on-off of a three-state gate G1; a three-state gate G1, wherein the input end of the three-state gate G1 is connected with the PWM output port of the control chip 1, the control end of the three-state gate G1 is connected with an output signal CTLTri of the control chip 1, and the output end of the three-state gate G1 is connected with a synchronizing signal Syn; a wiring terminal J which is used for accessing/outputting a synchronizing signal Syn; and a resistor R, wherein one end of the resistor R is connected with the synchronization signal Syn, and the other end of the resistor R is connected with the ground f |
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Bibliography: | Application Number: CN202011361485 |