PREFETCHING WEIGHTS FOR USE IN A NEURAL NETWORK PROCESSOR
A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inpu...
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Main Author | |
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Format | Patent |
Language | Chinese English |
Published |
09.03.2021
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Subjects | |
Online Access | Get full text |
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Summary: | A circuit for performing neural network computations for a neural network, the circuit comprising: a systolic array comprising a plurality of cells; a weight fetcher unit configured to, for each of the plurality of neural network layers: send, for the neural network layer, a plurality of weight inputs to cells along a first dimension of the systolic array; and a plurality of weight sequencer units, each weight sequencer unit coupled to a distinct cell along the first dimension of the systolic array, the plurality of weight sequencer units configured to, for each of the plurality of neural network layers: shift, for the neural network layer, the plurality of weight inputs to cells along the second dimension of the systolic array over a plurality of clock cycles and where each cell is configured to compute a product of an activation input and a respective weight input using multiplication circuitry.
本申请涉及用于对神经网络执行神经网络计算的电路,该电路包括:脉动阵列,该脉动阵列包括多个单元格;权重提取单元,对于多个神经网络层的每个神经网络层,该权重提取单元被配置为:对于该神经网络层,将多个权重输入发送到沿着脉动阵列的第一 |
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Bibliography: | Application Number: CN202011278833 |