Semiconductor integrated circuit device and process for fabricating the same

A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-...

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Bibliographic Details
Main Authors HIROHISA USUAMI, KAZUYUKI TSUNOKUNI, MASAYUKI KOJIMA
Format Patent
LanguageEnglish
Published 12.06.1996
Edition6
Subjects
ADVERTISING
BASIC ELECTRIC ELEMENTS
CRYPTOGRAPHY
DISPLAY
DISPLAYING
EDUCATION
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
LABELS OR NAME-PLATES
PHYSICS
SEALS
SEMICONDUCTOR DEVICES
SIGNS
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Summary:A process for forming an upper-layer fin and a lower-layer fin of a storage electrode, and a semiconductor integrated circuit device fabricated by the process. When two-layered polycrystalline silicon films are to be sequentially etched to form the upper-layer fin and the lower-layer fin by the dry-etching method using a first mask, the upper polycrystalline silicon film is patterned at first so far as to form the clearance of the upper-layer fins with the minimum working size of the memory cells of a DRAM, to form the upper-layer fin. Next, the lower-layer fin is formed by the dry-etching method using a second mask which has a pattern enlarged in self-alignment from the pattern of the first mask, so that it is given a larger horizontal size than that of the upper-layer fin.
Bibliography:Application Number: CN19951003555