Sub-threshold region low-power-consumption storage and calculation integrated CMOS circuit structure

• Main Authors: HU SHAOGANG, ZHOU TONG, LEI YULIN, LIU YANG, YU QI, DENG YANGJIE
• Format: Patent
• Language: Chinese; English
• Published: 19.02.2021
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; INFORMATION STORAGE; PHYSICS; STATIC STORES

The invention belongs to the technical field of computer architectures, and particularly relates to a sub-threshold region low-power-consumption storage and calculation integrated CMOS circuit structure. According to the current and voltage exponential relation when the MOSFETs work in a sub-threshold region, the single MOSFET outputs source and drain currents IDsub of different sizes under different source and drain voltages VDS and gate and source voltages VGS, and therefore additive operation of the source and drain voltages VDS and the gate and source voltages VGS in a current mode is completed while low-power-consumption design is achieved. On the basis of a single-bit storage module structure of a 6T SRAM, an operation module is added for operation realization, and a reading controlmodule is added for selective reading of an operation result. The operation module is provided with operation unit structures such as a current mode single-tube adder and the like, and outputs currents of different magnitudes