TRANSISTOR ARRAYS

• Main Authors: SOCRATOUS JOSEPHINE, VANDEKERCHOVE HERVE
• Format: Patent
• Language: Chinese; English
• Published: 05.02.2021
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive connections between levels, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drainconductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises: forming a first conductor subpattern which comprises conductor material at least in the regions of the addressing lines and provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductorsare in closest proximity; masking the first conductor subpattern in regions where the source and drain conductors are in closest proximity; thereafter forming a second conductor subpattern, which also comprises conductor mate