APPARATUSES, METHODS, AND SYSTEMS FOR MEMORY INTERFACE CIRCUIT ARBITRATION IN A CONFIGURABLE SPATIAL ACCELERATOR

• Main Authors: KAUSHIKKAR SUJOYITA, ZOU PING, CHOFLEMING KERMIN, DAYA BHAVYA K, VINOD KRISHNA N, SUPRUN ALEXEY, KAKADE ANIKET S
• Format: Patent
• Language: Chinese; English
• Published: 29.12.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

Systems, methods, and apparatuses relating to arbitration among a plurality of memory interface circuits in a configurable spatial accelerator are described. In one embodiment, a configurable spatialaccelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for improved memory sub-system design via arbitration and the improvements to arbitration discussed herein. 描述了用于存储器接口电路仲裁的装置、方法和系统。在一个实施例中，一种可配置空间加速器(CSA)包括多个处理元件；多个请求地址文件(RAF)电路，以及多个处理元件和RAF电路之间的电路交换互连网络。作为数据流体系结构，CSA的实施例具有独特的存储器体系结构，其中存储器访问被解耦合成显式的请求和响应阶段，允许了整个存储器中的管线化。这里的某些实施例经由本文论述的仲裁和对仲裁的改善来提供了改善的存储器子系统设计。