Processing device for distributing micro-operations to micro-operation cache and operation method thereof
Micro-operations (micro ops) are allocated into a micro op cache by dividing, by a micro branch target buffer (micro BTB), instructions into a first basic block in which the instructions are executedby a processing device and the first basic block corresponds to an edge of the instructions being exe...
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Main Author | |
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Format | Patent |
Language | Chinese English |
Published |
24.11.2020
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Subjects | |
Online Access | Get full text |
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Summary: | Micro-operations (micro ops) are allocated into a micro op cache by dividing, by a micro branch target buffer (micro BTB), instructions into a first basic block in which the instructions are executedby a processing device and the first basic block corresponds to an edge of the instructions being executed by the processing device. The micro BTB allocates the first basic block to an inverted basicblock queue (IBBQ) and the IBBQ determines that the first basic block fits into the micro op cache. The IBBQ allocates the first basic block to the micro op cache based on a number of times the edge of the instructions corresponding to the first basic block is repeatedly executed by the processing device.
通过由微分支目标缓冲区(μBTB)将指令划分到第一基本块而将微操作(μop)分配到μop高速缓存器中,其中指令由处理设备执行,并且第一基本块对应于处理设备执行的指令的边缘。μBTB将第一基本块分配给反向基本块队列(IBBQ),并且IBBQ确定第一基本块适合μop高速缓存器。IBBQ基于处理设备重复执行与第一基本块相对应的指令的边缘的次数,将第一基本块分配给μop高速缓存器。 |
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Bibliography: | Application Number: CN202010434520 |