Automatic clock phase synchronization in OTN multi-chassis system with fail over mechanism

• Main Authors: KULLASHETTY BASAVALINGA, SREENIVASAN ROHITH, KORI SIDDALINGAPRASAD, AYIKKARA NISHA, JAJU PIYUSH
• Format: Patent
• Language: Chinese; English
• Published: 04.09.2020
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; MULTIPLEX COMMUNICATION; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

A method is disclosed for use by a network element comprising a plurality of ports for communicating a common clock signal with one or more neighboring network elements. The method comprises, for at least one port of the plurality of ports, determining, while the port is in a predefined listening mode, whether the port is connected with a neighboring network element; and calculating, when the portis connected, a respective clock phase delay value between the network element and the neighboring network element. The method further comprises, based on a role assigned to the network element froma plurality of predefined roles, assigning a clock signal synchronization role to the port. The network element is configured to communicate the common clock signal using the respective clock phase delay value and using the clock signal synchronization role. 公开了一种用于由网络元件使用的方法，所述网络元件包括用于向一个或多个相邻网络元件传送公共时钟信号的多个端口。所述方法包括：对于多个端口中的至少一个端口：当所述端口处于预定义监听模式时，确定所述端口是否与相邻网络元件连接；以及当所述端口被连接时，计算所述网络元件和所述相邻网络元件之间的相应时钟相位延迟值。所述方法还包括基于从多个预定义