Deep learning hardware system based on systolic array architecture

• Main Authors: HE CHUNJIU, ZHANG XING, WANG XIN'AN, XU BOXING, YONG SHANSHAN
• Format: Patent
• Language: Chinese; English
• Published: 07.08.2020
• Subjects: CALCULATING; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL; PHYSICS

The embodiment of the invention belongs to the technical field of deep learning hardware architectures, and relates to a deep learning hardware system based on a systolic array architecture. The system comprises a data input and processing subsystem which is used for receiving and storing data and processing the data, whereinthe data comprises feature map data, convolution kernel data and configuration instruction data; asystolic array calculation subsystem which is used for performing line-by-line convolution operation on the feature map data and the convolution kernel data and outputting anoperation result; and acontrol subsystem which is used for controlling the pulsation array computing subsystem according to the configuration instruction data. The systolic array computing subsystem performs line-by-line parallel convolution operation on the feature map data and the convolution kernel data under the configuration and control of the control subsystem according to the configurationinstruction data; and unti