Heterogeneous multi-core processor for bus resource configuration adjustment

• Main Authors: ZHEN YAN, ZHOU YING, LIN LING, ZHENG LIBIN, CHEN WENBIN, LI DEJIAN, TAN NIANXIONG, YANG LIXIN, WANG YUANLONG, HUANG SUFANG
• Format: Patent
• Language: Chinese; English
• Published: 17.07.2020
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

The invention discloses a heterogeneous multi-core processor for bus resource configuration adjustment. The heterogeneous multi-core processor includes a first CPU, a bus device, a configuration bus connected with the first CPU, an architecture bus connected with the configuration bus, a DDR memory controller connected with a DDR memory, a first security control assembly connected with a first channel of the DDR memory controller, a first security control assembly connected with the configuration bus, and a second security control assembly connected with a second channel and a third channel ofthe DDR memory controller and the architecture bus; the configuration bus, the first security control assembly and the DDR memory controller form an access path for the first CPU to access the DDR memory. According to the technical scheme disclosed by the invention, the first CPU can access the DDR memory through the access path formed by the configuration bus and the like, so that the problem that the bandwidth is limit