Semiconductor process sheet and method for manufacturing semiconductor package

• Main Authors: SATO SATOSHI, SHIGA GOSHI, TAKAMOTO NAOHIDE
• Format: Patent
• Language: Chinese; English
• Published: 26.06.2020
• Subjects: ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; ADHESIVES; BASIC ELECTRIC ELEMENTS; CHEMISTRY; DYES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; LAYERED PRODUCTS; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM; METALLURGY; MISCELLANEOUS APPLICATIONS OF MATERIALS; MISCELLANEOUS COMPOSITIONS; NATURAL RESINS; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; PAINTS; PERFORMING OPERATIONS; POLISHES; SEMICONDUCTOR DEVICES; TRANSPORTING; USE OF MATERIALS AS ADHESIVES

This semiconductor process sheet is provided with a double-sided adhesive sheet (10) and a partial sealing agent layer (20). The double-sided adhesive sheet (10) includes, in a laminated structure between adhesive surfaces (10a, 10b) thereof, a base material (11), a reduced adhesiveness-type adhesive agent layer (12), and, for example, a pressure-sensitive adhesive agent layer (13). The partial sealing agent layer (20) is positioned on the adhesive surface (10b) of the double-sided adhesive sheet (10). This method includes, for example: a step for mounting a plurality of semiconductor chips onthe partial sealing agent layer (20) of the semiconductor process sheet having the adhesive surface (10a) adhered to a supporting body; a step for forming a sealing member section by curing the partial sealing agent layer (20) and a sealing agent, which is supplied so as to embed the semiconductor chips; a step for separating the sealing member section and the adhesive surface (10b); a step for forming a wiring structure