BARRIER REDUCTION DURING CODE TRANSLATION

Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a m...

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Bibliographic Details
Main Authors KISHAN ARUN UPADHYAYA, DANG CLARENCE SIU YEEN
Format Patent
LanguageChinese
English
Published 12.06.2020
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:Reducing emission of barriered instructions when translating processor instructions between instruction set architectures (ISA's). Embodiments include obtaining block(s) of processor instructions formatted according to a first processor ISA. The block(s) include an instruction that performs a memory operation whose execution order is constrained based on a hardware memory model of the first processor ISA. Based on an analysis of the block(s) of processor instructions, it is determined that the memory operation of the at least one instruction can be made order-independent in a hardware memory model of a second processor ISA. Based on the determination, one or more unbarriered processor instructions that are formatted according to the second processor ISA are emitted. The unbarriered processor instruction(s) are structured to perform the memory operation without ordering constraint. 当在指令集架构(ISA)之间转换处理器指令时减少被屏障指令的发出。实施例包括获取根据第一处理器ISA被格式化的(多个)处理器指令块。(多个)块包括执行存储器操作的指令，该存储器操作的执行次序基于第一处理器ISA的硬件存储器模型而被约束。基于对(多个)处理器指令
Bibliography:Application Number: CN201880067059