INTERFACE CHIP, AND STORAGE DEVICE INCLUDING INTERFACE CHIP AND MEMORY CHIP

• Main Authors: LEE JANGWOO, CHO HWASUK, YANG MANJAE, IHM JEONGDON
• Format: Patent
• Language: Chinese; English
• Published: 02.06.2020
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

An interface chip includes a command decoder configured to decode a command included in data input/output signals based on a clock signal, clock masking circuitry configured to generate a masking clock signal including an edge corresponding to a first edge among first to n-th edges of the clock signal (n being an integer of 2 or more), clock latency circuity configured to transmit, to an externalchip, a latency clock signal including edges corresponding to the second to n-th edges of the clock signal, chip select circuitry configured to generate a chip select signal based on an address included in the data input/output signals and the masking clock signal, and chip enable control circuitry configured to receive a chip enable signal indicating a channel for the data input/output signals and transmit the chip enable signal to the external chip based on the chip select signal. 一种接口芯片包括：命令解码器，被配置为基于时钟信号解码被包括在数据输入/输出信号中的命令；时钟掩蔽电路，被配置为生成掩蔽时钟信号，该掩蔽时钟信号包括与时钟信号的第一边沿至第n边沿(n是2或更大的整数)当中的第一边沿相对应的边沿；时钟延迟电路，被配置为向外部芯片发送延迟时钟信