MEMORY CONTROLLER AND OPERATING METHOD THEREOF
A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed...
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Main Authors | , |
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Format | Patent |
Language | Chinese English |
Published |
29.05.2020
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Subjects | |
Online Access | Get full text |
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Summary: | A memory controller having an improved operation speed controls a memory device including a plurality of memory blocks. The memory controller includes: a remaining count determiner configured to determine a remaining count that is a number of program and erase operations to be additionally performed in the memory device based on a program/erase count received from the memory device, a retention period calculator configured to determine a retention period based on a power-off time and a power-on time of the memory device and a read voltage determiner configured to generate a changed read voltage table based on a default read voltage table and a coefficient determined according to the remaining count, and determine a read voltage to be used in the memory device according to the retention period among read voltages included in the changed read voltage table.
本发明涉及一种操作速度提高的存储器控制器,该存储器控制器控制包括多个存储块的存储器装置。该存储器控制器包括:剩余计数确定器,被配置成基于从存储器装置接收的编程/擦除计数来确定剩余计数,该剩余计数为待在存储器装置中另外地执行的编程操作和擦除操作的数量;保留时段计算器,被配置成基于存储器装置的断电时间和通电时间来确 |
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Bibliography: | Application Number: CN201910827923 |