PATTERING SEMICONDUCTOR FOR TFT DEVICE

A technique, comprising: forming, over a substrate (2) comprising at least source and drain conductors (4, 6) for one or more transistor devices, at least a first, semiconductor layer (8) providing one or more semiconductor channels for the one or more transistor devices; forming, over the first lay...

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Bibliographic Details
Main Authors DURY JOFFREY, VANDEKERCKHOVE HERVE
Format Patent
LanguageChinese
English
Published 12.05.2020
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Summary:A technique, comprising: forming, over a substrate (2) comprising at least source and drain conductors (4, 6) for one or more transistor devices, at least a first, semiconductor layer (8) providing one or more semiconductor channels for the one or more transistor devices; forming, over the first layer, a second layer (10) that defines at least part of a gate dielectric for the one or more transistor devices; creating a pattern in the second layer, without depositing any temporary material onto the second layer; and using the pattern in the second layer to pattern the first layer. 一种技术,包含以下步骤:在包含用于一或多个晶体管装置之至少源极与漏极导体(4,6)之基体(2)上方形成半导体的至少一第一层(8),其提供用于所述一或多个晶体管装置的一或多个半导体通道;在所述第一层上方形成界定用于所述一或多个晶体管装置之栅极介电体之至少一部分的第二层(10);在所述第二层中生成图案,而不沉积任何暂时性材料到所述第二层上;及使用所述第二层中的所述图案来图案化所述第一层。
Bibliography:Application Number: CN201880062491