Method and device for improving DDR storage bus utilization rate

The invention provides a method for improving DDR (Double Data Rate) storage bus utilization rate, which comprises the following steps of: (1) receiving a command, caching according to a command entrysequence to form a command cache queue, and outputting the command to a DDR memory; (2) recording a...

Full description

Saved in:
Bibliographic Details
Main Authors HUANG NIANZHI, SONG CHAO
Format Patent
LanguageChinese
English
Published 22.10.2019
Subjects
Online AccessGet full text

Cover

Loading…
More Information
Summary:The invention provides a method for improving DDR (Double Data Rate) storage bus utilization rate, which comprises the following steps of: (1) receiving a command, caching according to a command entrysequence to form a command cache queue, and outputting the command to a DDR memory; (2) recording a command sequence and accessed address information in the command cache queue while forming the command cache queue; (3) recording command address information output from the command cache queue, starting timing, and feeding back a timing result and bank information; and (4) screening according to the command sequence and access address information in the command cache queue recorded in the step (2) and the result fed back in the step (3), searching the same bank and same row command, and advancing the same bank and same row command to the front end of the command cache queue. The invention further provides a device for improving the DDR storage bus utilization rate. The device is composed of a command cache queue m
Bibliography:Application Number: CN201910667456