DATA RETENTION CIRCUIT AND METHOD

• Main Authors: SHANGIH HSIEH, LEEUNG LU, WEI-HSIANG MA, KAII HUANG, CHI-LIN LIU, JERRY CHANG-JUI KAO, YUNGN CHIEN
• Format: Patent
• Language: Chinese; English
• Published: 18.10.2019
• Subjects: BASIC ELECTRONIC CIRCUITRY; ELECTRICITY; PULSE TECHNIQUE

The embodiment of the invention provides a data retention circuit and method. The circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch,and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level,the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includesa level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other one of the first power supply voltage level orthe second power supply voltage level. 本发明的实施例提供了数据保持电路以及方法。电路包括从锁存器，从锁存器包括第一输入端和输出端，第一输入端连接至主锁存器，以及保持锁存器，保持锁存器包括连接至输出端的第二输入端。主锁存器和从锁存器被配置为在具有第一电源电压电平的第一电源域中工作，保持锁存器被配置为在具有与第一电源电压电平不同的第二电源电压电平的第二电源域中工作，以及该电路还包括电平移位器，该电平移位器被配置为将